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INTEGRATED CIRCUITS
SSTV16859 2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
Product data 2000 Dec 01 File under Integrated Circuits -- ICL03 2002 Feb 19
Philips Semiconductors
Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
FEATURES
* Stub-series terminated logic for 2.5 V VDD (SSTL_2) * Optimized for stacked DDR (Double Data Rate) SDRAM
applications
DDR (Double Data Rate) SDRAM and SDRAM II Memory Modules. Different from traditional SDRAM, DDR SDRAM transfers data on both clock edges (rising and falling), thus doubling the peak bus bandwidth. A DDR DRAM rated at 133 MHz will have a burst rate of 266 MHz. The device data inputs consist of different receivers. One differential input is tied to the input pin while the other is tied to a reference input pad, which is shared by all inputs. The clock input is fully differential (CK and CK) to be compatible with DRAM devices that are installed on the DIMM. Data are registered at the crossing of CK going high, and CK going low. However, since the control inputs to the SDRAM change at only half the data rate, the device must only change state on the positive transition of the CK signal. In order to be able to provide defined outputs from the device even before a stable clock has been supplied, the device has an asynchronous input pin (RESET), which when held to the LOW state, resets all registers and all outputs to the LOW state. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power-up. In the DDR DIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering RESET, the register will be cleared and the outputs will be driven low. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the outputs will remain low. Available in 64-pin plastic thin shrink small outline package.
* Supports SSTL_2 signal inputs as per JESD 8-9 * Flow-through architecture optimizes PCB layout * ESD classification testing is done to JEDEC Standard JESD22.
Protection exceeds 2000 V to HBM per method A114.
* Latch-up testing is done to JEDEC Standard JESD78, which
exceeds 100 mA.
* Supports efficient low power standby operation * Full DDR 200/266 solution for stacked DIMMs at 2.5 V when used
with PCKV857
* See SSTV16857 for JEDEC compliant register support in
unstacked DIMM applications
* See SSTV16856 for driver/buffer version with mode select.
DESCRIPTION
The SSTV16859 is a 13-bit to 26-bit SSTL_2 registered driver with differential clock inputs, designed to operate between 2.3 V and 2.7 V. All inputs are compatible with the JEDEC standard for SSTL_2 with VREF normally at 0.5*VDD, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible which can be used for standard stub-series applications or capacitive loads. Master reset (RESET) asynchronously resets all registers to zero. The SSTV16859 is intended to be incorporated into standard DIMM (Dual In-Line Memory Module) designs defined by JEDEC, such as
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25C; tr = tf v2.5 ns SYMBOL tPHL/tPLH CI PARAMETER Propagation delay; CLK to Qn Input capacitance CONDITIONS CL = 30 pF; VDD = 2.5 V VCC = 2.5 V TYPICAL 2.4 2.7 UNIT ns pF
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; (CL x VCC2 x fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES 64-Pin Plastic TSSOP 96-Ball Plastic LFBGA 56-Terminal Plastic HVQFN TEMPERATURE RANGE 0 to +70 C 0 to +70 C 0 to +70 C ORDER CODE SSTV16859DGG SSTV16859EC SSTV16859BS DWG NUMBER SOT646AA1 SOT536-1 SOT684-1
2002 Feb 19
2
853-2233 27756
Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
PIN CONFIGURATION
PIN DESCRIPTION
PIN NUMBER 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 16 17, 19, 20, 21, 22, 23, 24, 25, 28, 29, 30, 31, 32 6, 18, 27, 33, 37, 38, 46, 47, 59, 60, 64 7, 15, 26, 34, 39, 43, 50, 54, 58, 63 35, 36, 40, 41, 42, 44, 52, 53, 55, 56, 57, 61, 62 45 48, 49 SYMBOL Q13A-Q1A NAME AND FUNCTION Data output
Q13A Q12A Q11A Q10A Q9A VDD GND Q8A Q7A
1 2 3 4 5 6 7 8 9
64 VDD 63 GND 62 D13 61 D12 60 VDD 59 VDD 58 GND 57 D11 56 D10 55 D9 54 GND 53 D8 52 D7 51 RESET 50 GND 49 CK 48 CK 47 VDD 46 VDD 45 VREF 44 D6 43 GND 42 D5 41 D4 40 D3 39 GND 38 VDD 37 VDD 36 D2 35 D1 34 GND 33 VDD
Q13B-Q1B
Data output
VDD
Power supply voltage
GND
Ground
Q6A 10 Q5A 11 Q4A 12 Q3A 13 Q2A 14 GND 15 Q1A 16 Q13B 17 VDD 18 Q12B 19 Q11B 20 Q10B 21 Q9B 22 Q8B 23 Q7B 24 Q6B 25 GND 26 VDD 27 Q5B 28 Q4B 29 Q3B 30 Q2B 31 Q1B 32
D1-D13
Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK Input reference voltage Positive and negative master clock input Asynchronous reset input: resets registers and disables data and clock differential input receivers
VREF CK, CK
51
RESET
SW00749
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Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
56-TERMINAL CONFIGURATION
Q10A Q12A Q11A Q13A VDDQ VDDQ VDDQ GND Q8B Q9A VDDI D13 D12 D11
TERMINAL DESCRIPTION
TERMINAL NUMBER 1, 2, 3, 4, 5, 6, 7, 50, 51, 52, 53, 54, 56 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22 9, 17, 23, 27, 34, 44, 49, 55 26, 33, 45 37, 48 24, 25, 28, 29, 30, 31, 39, 40, 41, 42, 43, 46, 47 32 35, 36
SW01040
SYMBOL
NAME AND FUNCTION
56
55
54
53
52
51
50
49
48
47
46
45
44
43
Q13A-Q1A
Data output
Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ
1 2 3 4 5 6 7 8 9
42 D10 41 D9 40 39 38 D8 D7 RESET
Q13B-Q1B
Data output
37 GND 36 CLK VDDQ VDDI VREF
VDDQ VDDI GND
Power supply voltage Power supply voltage Ground Data input: clocked in on the crossing of the rising edge of CK and the falling edge of CK Input reference voltage Positive and negative master clock input Asynchronous reset input: resets registers and disables data and clock differential input receivers
35 CLK 34 33 32
Q12B 10 Q11B 11 Q10B 12 Q9B 13 Q8B 14 Q7B 15 Q6B 16 VDDQ 17 Q5B 18 Q4B 19 Q3B 20 21 22 VDDQ 23 D1 24 D2 25 VDDI 26 27 D3 28
D1-D13
31 D6 30 D5 29 D4
VREF CK, CK
Q2B
Q1B
VDDQ
51
RESET
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Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
BALL CONFIGURATION
1 A B C D E F G H J K L M N P R -- Q12A Q10A Q8A Q6A Q4A Q2A Q1A Q12B Q10B Q8B Q6B Q4B Q2B -- 2 -- Q13A Q11A Q9A Q7A Q5A Q3A Q13B Q11B Q9B Q7B Q5B Q3B Q1B -- 3 -- GND GND VDDQ VDDQ VDDQ GND GND GND VDDQ VDDQ VDDQ GND GND -- 4 -- GND GND VDDQ VDDQ VDDQ GND GND VREF VDDQ VDDQ VDDQ GND GND -- 5 -- -- -- D13 D11 D9 D7 -- -- -- D5 D3 D1 -- -- 6 -- -- -- D12 D10 D8 RESET CK CK -- D6 D4 D2 -- --
T
--
--
--
--
--
--
SW00944
LOGIC DIAGRAM
RESET 51 16
H H H
1D Q1A
L or H X or floating
# # L or H X or floating
L H X X or floating
L H Q0 L
L
CK CK D1 VREF
48 49 35 45 C1 32 R Q1B
H = High voltage level L = Low voltage level = High-to-Low transition = Low-to-High transition X = Don't care
to 12 other channels
SW00750
FUNCTION TABLE (each flip flop)
INPUTS RESET CLK CLK D OUTPUT Q
2002 Feb 19
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Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
ABSOLUTE MAXIMUM RATINGS1
SYMBOL VDD VI VO IIK IOK IO PARAMETER Supply voltage range Input voltage range Output voltage range Input clamp current Output clamp current Continuous output current Continuous current through each VDD or GND Tstg Storage temperature range Notes 2 and 3 Notes 2 and 3 VI < 0 or VI > VDD VO < 0 or VO > VDD VO = 0 to VDD CONDITION LIMITS MIN -0.5 -0.5 -0.5 -- -- -- -- -65 MAX +3.6 VDD + 0.5 VDD + 0.5 50 50 50 100 +150 UNIT V V V mA mA mA mA C
NOTES: 1. Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 3. This value is limited to 3.6 V maximum. 4. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures that are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C.
RECOMMENDED OPERATING CONDITIONS1
SYMBOL VDD VREF VTT VI VIH VIL VIH VIL VIH VIL VICR VID IOH IOL Tamb PARAMETER Supply voltage Reference voltage (VREF = VDD/2) Termination voltage Input voltage AC HIGH-level input voltage AC LOW-level input voltage DC HIGH-level input voltage DC LOW-level input voltage HIGH-level input voltage LOW-level input voltage Common-mode input range Differential input voltage HIGH-level output current LOW-level output current Operating free-air temperature range CK, CK CK, CK Data inputs Data inputs Data inputs Data inputs RESET CONDITIONS MIN VDD 1.15 VREF - 40 mV 0 VREF + 310 mV -- VREF + 150 mV -- 1.7 0.0 0.97 360 -- -- 0 TYP -- 1.25 VREF -- -- -- -- -- -- -- -- -- -- -- -- MAX 2.7 1.35 VREF + 40 mV VDD -- VREF - 310 mV -- VREF - 150 mV VDD 0.7 1.53 -- -20 20 +70 UNIT V V V V V V V V V V V mV mA mA C
NOTE: 1. The RESET input of the device must be held at VDD or GND to ensure proper device operation. The differential inputs must not be floating, unless RESET is low.
2002 Feb 19
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Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions. Voltages are referenced to GND (ground = 0 V). LIMITS SYMBOL VIK VO OH VO OL II IDD All inputs Static standby Static operating Dynamic operating - clock only IDDD Dynamic operating - per each data input rOH rOL rO() Output high Output low |rOH - rOL| each separate bit Data inputs Ci CK and CK RESET PARAMETER TEST CONDITIONS II = -18 mA, VDD = 2.3 V IOH = -100 A, VDD = 2.3 to 2.7 V IOH = -16 mA, VDD = 2.3 V IOL = 100 A, VDD = 2.3 to 2.7 V IOL = 16 mA, VDD = 2.3 V VI = VDD or GND, VDD = 2.7 V RESET = GND RESET = VDD, VI = VIH(AC) or VIL(AC) RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. RESET = VDD, VI = VIH(AC) or VIL(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle. IOH = -20 mA, VDD = 2.3 to 2.7 V IOL = 20 mA, VDD = 2.3 to 2.7 V IO = 20 mA, Tamb = 25C, VDD = 2.5 V VI = VREF 310 mV, VDD = 2.5 V VICR = 1.25 V, VI(PP) = 360 mV, VDD = 2.5 V VI = VDD or GND, VDD = 2.5 V IO = 0, VDD = 2.7 V 20 -- -- A/ clock MHz/ data input IO = 0, VDD = 2.7 V Tamb = 0 to +70 C MIN -- VDD - 0.2 1.95 -- -- -- -- -- 90 TYP -- -- -- -- -- -- -- -- -- MAX -1.2 -- -- 0.2 0.35 5 0.01 45 -- mA V V V A UNIT
A/ clock MHz
7 7 -- 2.5 2.5 --
-- -- -- 2.74 3.15 2.27
20 20 4 3.5 3.5 --
pF
2002 Feb 19
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Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
TIMING REQUIREMENTS
Over recommended operating conditions; Tamb = 0 to +70 C (unless otherwise noted) (see Figure 1) LIMITS SYMBOL PARAMETER TEST CONDITIONS VDD = 2.5 V 0.2 V MIN fclock tw tact tinact Clock frequency Pulse duration, CK, CK HIGH or LOW Differential inputs active time Differential inputs inactive time Setup time, fast slew rate (see Notes 4 and 6) Setup time, slow slew rate (see Notes 5 and 6) Hold time, fast slew rate (see Notes 4 and 6) Hold time, slow slew rate (see Notes 5 and 6) Output slew Notes 1, 2 Notes 1, 3 -- 2.5 -- -- 0.75 Data before CK, CK CK 0.9 0.75 Data after CK, CK CK 0.9 1 6 V/ns ns ns MAX 200 -- 22 22 MHz ns ns ns UNIT
tsu
th
tSL
NOTES: 1. This parameter is not necessarily production tested. 2. Data inputs must be below a minimum time of tact max, after RESET is taken high. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET is taken low. 4. For data signal input slew rate 1 V/ns. 5. For data signal input slew rate 0.5 V/ns and < 1 V/ns. 6. CK, CK signals input slew rates are 1 V/ns.
SWITCHING CHARACTERISTICS
Over recommended operating conditions; Tamb = 0 to +70 C; VDD = 2.3 - 2.7 V. Class I, VREF = VTT = VDD x 0.5 and CL = 10 pF (unless otherwise noted) (see Figure 1) LIMITS SYMBOL FROM O (INPUT) TO O (OUTPUT) VDD = 2.5 V 0.2 V MIN fmax tpd tPHL CK and CK RESET Q Q 200 1.1 1.1 MAX -- 2.8 5 MHz ns ns UNIT
2002 Feb 19
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Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
OUTPUT BUFFER CHARACTERISTICS
The following table describes output-buffer Voltage vs. Current (V/I) characteristics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these curves is not mandatory if it can be adequately demonstrated that alternate characteristics meet the requirements of the registered DDR DIMM application. VOLTAGE (V) I (mA) MIN 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 0 7 14 21 28 33 39 44 48 52 56 59 61 63 64 66 66 67 67 67 67 68 68 68 -- -- -- -- PULL-DOWN I (mA) MAX 0 11 23 34 44 54 64 74 83 91 99 107 114 121 127 133 138 142 146 149 151 153 154 155 156 157 157 157 I (mA) MIN 0 7 14 21 27 33 38 44 49 53 57 61 64 67 69 70 72 73 74 74 75 75 75 76 -- -- -- -- PULL-UP I (mA) MAX 0 10 20 30 40 49 59 68 76 84 93 100 108 115 121 128 134 139 144 148 152 156 159 161 163 165 167 168
PARAMETER MEASUREMENT INFORMATION TEST CIRCUIT
From Output RL = 50 Test Point Under Test CL = 30 pF see Note 1
SW00751
Figure 1. Load circuitry NOTE: 1. CL includes probe and jig capacitance.
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Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
AC WAVEFORMS
LVCMOS RESET VDD/2 VDD/2 tact 90% IDD 10% tPHL VDD LVCMOS RESET Input VDD/2 VIL VIH
tinact
SW00752
Waveform 1. Inputs active and inactive times (see Note 1)
Output VTT
VOH
VOL tW VIH INPUT VREF VREF VIL Timing input
SW00755
Waveform 4. Propagation delay times
SW00753
VICR
VI(PP)
Waveform 2. Pulse duration
tsu TIMING INPUT VICR VICR VI(PP) Input VREF
th VIH VREF VIL
tPLH
tPHL
VOH OUTPUT VTT VOL
SW00756
Waveform 5. Setup and hold times
SW00754
Waveform 3. Propagation delay times NOTES: 1. IDD tested with clock and data inputs held at VDD or GND, and IO = 0 mA. 2. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , input slew rate = 1 V/ns 20% (unless otherwise specified). 3. The outputs are measured one at a time with one transition per measurement. 4. VTT = VREF = VDD/2 5. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 6. VIL = VREF - 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH and tPHL are the same as tpd.
2002 Feb 19
10
Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
TSSOP64: plastic thin shrink small outline package; 64 leads; body width 6.1 mm
SOT646-1
2002 Feb 19
11
Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm
SOT536-1
2002 Feb 19
12
Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
HVQFN56: plastic, heatsink very thin quad flat package; no leads; 56 terminals; body 8 x 8 x 0.85 mm
SOT684-1
2002 Feb 19
13
Philips Semiconductors
Product data
2.5 V 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM
SSTV16859
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 02-02
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 09464
Philips Semiconductors
2002 Feb 19 14

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